GigaDevice Unveils GD32V Series with RISC-V Core

GigaDevice unveils the GD32V series with RISC-V core, in a brand new 32bit general purpose microcontroller Adopt the GD32V series 32-bit general purpose MCU and discover the RISC-V development world now! GigaDevice Semiconductor, has officially launched the world’s first open source RISC-V based GD32V series 32-bit general-purpose MCU products. GigaDevice provides a complete tool chain support from MCU chips to software libraries and development boards; therefore, creating a strong RISC-V development ecosystem. As the first product line of the GD32 MCU family based on the RISC-V core, the new GD32VF103 series RISC-V MCU is designed for mainstream development needs, providing a cost-effective and innovative choice, whilst entering the mainstream market with balanced processing performance and system resources. The new products are available in 14 models, including QFN36, LQFP48, LQFP64 and LQFP100, and are fully compatible with existing GD32 MCUs in software development and pin packaging. This unprecedented and innovative design accelerates the development cycle between GD32’s Arm® core and RISC-V core products, making product selection and code porting flexible and simple. The new products are specifically targeted for embedded applications ranging from industrial control, consumer electronics, emerging IOT, edge computing to artificial intelligence and deep learning. Fully optimized RISC-V processor core The GD32VF103 MCU series adopts the new Bumblebee processor core based on the open source RISC-V instruction set architecture. It is jointly developed by GigaDevice and China’s leading RISC-V processor core IP and solution manufacturer Nuclei System Technology, offering a commercial RISC-V processor core for IoT and ultra-low power applications. The Bumblebee core uses a 32-bit RISC-V open source instruction set architecture and supports custom instructions to optimize interrupt handling. It is not only equipped with a 64-bit wide real-time timer, but also it can generate timer interrupts defined by the RISC-V standard, with support of dozens of external interrupt sources, while possessing 16 interrupt levels and priorities, interrupt nesting and fast vector interrupts processing mechanism. Furthermore, the low-power management unit can support two-levels of sleep mode. The core supports standard JTAG interfaces and RISC-V debug standards for hardware breakpoints and interactive debugging. Additionally, the Bumblebee core supports the RISC-V standard compilation tool chain, as well as Linux/Windows graphical integrated development environment. The Bumblebee core is designed with a two-stage variable-length pipeline microarchitecture with a streamlined dynamic branch predictor and instruction prefetch unit, while it incorporates a variety of low-power design methods. The performance and frequency of the traditional architecture three-stage pipeline can be achieved at the cost of the two-stage pipeline, achieving industry-leading energy efficiency and cost advantages. These features allow the GD32VF103 MCU series to operate at up to 153 DMIPS at the highest frequency and under the CoreMark® test achieves 360 performance points, which shows 15% performance improvement compared to the GD32 Cortex®-M3 core. At the same time, the dynamic power consumption is reduced by 50% and the standby power consumption is reduced by 25%.